A frequency prescaler is designed to be used upstream from a programmable counter. The frequency divider constituted by those two elements taken together needs to be capable of performing division by a selected overall division ratio (written D below).
The divider of the invention particularly, but not exclusively, is designed for implementation in a phase-locked loop frequency synthesizer. Such a synthesizer comprises a frequency divider enabling the output frequency f.sub.s of the synthesizer to be divided by D so as to obtain the feedback loop frequency f.sub.b. In other words, f.sub.b =f.sub.s /D.
The loop frequency f.sub.b and the comparison frequency f.sub.c constitute respective ones of two inputs to the phase comparator included in the frequency synthesizer.
The output frequency f.sub.s of the synthesizer is either equal to the radio frequency or is n times greater than the radio frequency (for reasons given below). The radio frequency is a variable frequency lying within a predetermined range. It is incremented in steps of a size that corresponds to the bandwidth of a radio channel. The idea is to be able to generate all of the existing radio channels, and it is specifically by acting on the overall division ratio D of the frequency divider that it is possible to switch from one radio channel to another.
In the context of the present invention, the prescaler is considered as operating with a pair of division ratios, written k/k+1, and referred to as the operating pair in the description below. The prescaler has means for changing over between the higher division ratio k+1 to the lower division ratio k in the operating pair k/k+1, as a function of a changeover signal (also known as a "modulus control" signal).
In general terms, the overall division ratio D of a frequency divider can be written D=k.N+A, where:
N is a first predetermined programmable value corresponding to the division ratio of the programmable counter; and PA1 A is a second predetermined programmable value which, on being reached by the programmable counter, causes the prescaler to receive the changeover signal. It should be observed that it is necessary for the relationship 0.ltoreq.A&lt;N to be satisfied. PA1 either both division ratios in the pair of prescaler division ratios k/k+1 remain unchanged and the division ratio of the programmable counter is multiplied by n; or PA1 the pair of division ratios k/k+1 of the prescaler is multiplied by n (if n=2, then the pair k'/k'=1 is used, where k'=2.k), and the division ratio of the programmable counter remains unchanged. PA1 for N=64: 8192.ltoreq.D.ltoreq.8255;(division ratios 8256 to 8319 are missing) PA1 for N=65: 8320.ltoreq.D.ltoreq.8384;(division ratios 8385 to 8447 are missing) PA1 for N=66: 8448.ltoreq.D.ltoreq.8513; PA1 etc. PA1 said prescaler being of the type that operates with a pair of division ratios, written k/k+1, and including means for changeover from the higher division ratio k+1to the lower division ratio k of said operating pair k/k+1as a function of a modulus control signal, PA1 N being a first predetermined programmable value corresponding to the division ratio of said programmable counter, and PA1 A being a second predetermined programmable value such that on being reached by the programmable counter, the prescaler receives said modulus control signal, with the relationship 0.ltoreq.A&lt;N necessarily being satisfied; PA1 wherein said prescaler has at least two successive pairs of division ratios, written respectively p/p+1, p+1/p+2, p+2/p+3, etc., and PA1 wherein said prescaler includes selection means for dynamically selecting one of said pairs of division ratios as a function of a selection signal, the selected pair constituting said operating pair k/k+1, said selection signal depending on said overall division ratio D that said frequency divider is to apply. PA1 p is the smaller division ratio of the first of said successive pairs of division ratios p/p+1, p+1/p+2, p+2/p+3, etc.; PA1 S is a function such that S(x) is the first integer greater than or equal to x; and PA1 c is the number of successive pairs of division ratios p/p+1,p+1/p+2, p+2/p+3, etc. PA1 a phase comparator receiving both a loop frequency f.sub.b and a comparison frequency f.sub.c which is obtained from a clock frequency f.sub.h as delivered by a resonant element; PA1 a loop filter receiving the output from said phase comparator; PA1 a voltage controlled oscillator receiving the output from said loop filter, and generating the output frequency f.sub.s of said synthesizer; and PA1 programmable divider means dividing said output frequency f.sub.s to obtain said loop frequency f.sub.b ;
It will be observed that frequency dividers must be capable of receiving and thus of working at ever-increasing frequencies.
Thus, it is now commonplace for the output frequency f.sub.s of a synthesizer (i.e. the frequency which the frequency divider must divide by D so as to obtain the loop frequency f.sub.b)to be a frequency that is n times greater than the radio frequency. This makes it possible to solve problems of shielding associated with direct transposition, and to improve phase noise, providing that comparison also takes place at a multiple frequency.
In other words, it is now the practice to use an output frequency f.sub.s from the synthesizer and a comparison frequency f.sub.c both of which are multiples of the frequencies that used to be used in the past (e.g. n times greater).
This known technique, which consists in using an output frequency f.sub.s and a comparison frequency f.sub.c that are multiples of those used in the past, is described below both for the GSM 900 case ("Global system for mobile communication operating in the 900 MHz band") and in the DCS 1800 case ("Digital communication system" operating in the 1800 MHz band).
In the GSM 900 standard, the radio frequency band lies around 900 MHz. By selecting, by way of example, a synthesizer that gives an output frequency f.sub.s that is four times greater than the radio frequency, i.e. f.sub.s =4.times.900 MHz=3.6 GHz, it is possible to obtain a synthesizer having phase noise that is much lower if the comparison frequency is likewise four times greater than the present comparison frequency, i.e. f.sub.c =4.times.200 kHz=800 kHz.
In the DCS 1800 standard, the radio frequency band lies around 1.8 GHz. By selecting, for example, a synthesizer delivering an output frequency f.sub.s that is twice as high as the radio frequency, i.e. f.sub.s =2.times.1800 MHz=3.6 GHz, then the synthesizer will give much lower phase noise if the comparison frequency is likewise twice as high as the present comparison frequency, i.e. f.sub.c 2.times.200 kHz=400 kHz.
This multiplication by n of the output frequency f.sub.s and of the comparison frequency f.sub.c has no effect on the overall division ratio D that the divider needs to apply for a desired radio channel of frequency f.sub.r. Because the loop frequency f.sub.b converges on the comparison frequency f.sub.c, using an output frequency f.sub.s and a comparison frequency f.sub.c that are n times greater than before amounts to using an output frequency f.sub.s and a loop frequency f.sub.b that are n times greater than before. Consequently, to obtain a given radio channel of radio frequency f.sub.r, the overall division ratio D of the divider remains unchanged since D=f.sub.s /f.sub.b =n.f.sub.s /n.f.sub.b.
In contrast, multiplying the output frequency f.sub.s and the comparison frequency f.sub.c in this way by n is not without its effects on the hardware. The frequency which the divider receives is multiplied by n. Consequently, since the overall division ratio D is unaffected, two solutions can be envisaged:
Unfortunately, both of those two solutions suffer from drawbacks.
With the first solution, the programmable counter receives a frequency that is n times higher than that which it receives at present. Thus, with n=2, the frequency input to the programmable counter will be 60 MHz instead of the present 30 MHz. Unfortunately, such an increase in frequency is not always possible because the programmable counter is generally implemented in CMOS and has a limited operating speed. In other words, the programmable counter is designed for "low frequency" operation. In any event, even if the programmable counter can accommodate such an increase in the frequency it receives, that can only be achieved at the cost of a large increase in power consumption, and possibly also with repercussions on noise in the phase-locked loop, because of the smaller ratio between the maximum frequency that the technology can accommodate and the frequency at which it actually operates.
It is therefore normal practice to seek to increase the division ratios of the prescaler (the second of the above-mentioned solutions). From the formula D=k.N+A, A needs to be capable of varying over the range 0 to k-1 in order to make it possible to implement all division ratios D (i.e. so that all channels can be addressed). Unfortunately, because of the relationship 0.ltoreq.A&lt;N, A cannot vary over the range 0 to k-1 if N&lt;k-1(since under such circumstances that would give A&lt;N&lt;k-1). In other words, if N&lt;k-1, then it is not possible to provide all of the necessary division ratios.
For example, with k=128, then N.sub.min =64. From the formula D=k.N+A, and from the relationship 0.ltoreq.A.ltoreq.N-1, it can be deduced that k.N.ltoreq.D.gtoreq.k.N+(N-1). Thus, taking successive values of N from N.sub.min, the following are obtained:
Thus, in this example, division ratios 8256 to 8319, 8385 to 8447, etc. cannot be implemented.
To sum up, it would appear that present frequency dividers are incapable of satisfying the new requirement of operating at ever-increasing frequency.